Digital processing and communication systems have continued to rapidly increase in speed. This increase in speed has brought with it increasingly tighter constraints that are imposed upon integrated circuits (ICs) used in such systems. Whether a given IC meets such constraints is controlled in significant part by how well the IC's processing parameters conform to target values. Threshold voltages, doping concentrations, and resistance values of the various layers that makeup a modem IC, just to name a few examples, can all affect whether an IC conforms to a given set of constraints. These parameters all affect the operational speed of individual devices within an IC.
One way that the speed or performance of the devices within an IC can be described is by way of what is known as “process corners.” These corners describe the speed of a device or combination of devices measured at different operating condition extremes. Several operating parameters can be used to define a corner, such as, for example, temperature and voltage. Thus, for example, a resistive device and a capacitive device coupled in series can be used as a reference circuit within an IC, wherein the pre-charge and discharge rates of the circuit are measured under differing temperature and voltage conditions. The measured performance, when compared to the target or expected performance, provides a measure of how close one or more of the processing parameters of the IC are to their target values in the final operational IC.
In the case of complimentary metal-oxide semiconductor (CMOS) ICs, process corners are described in terms of the speed of metal-oxide semiconductor (MOS) devices with positively doped channels (PMOS devices), and MOS devices with negatively doped channels (NMOS devices), as well as in terms of the device structures used to measure the performance of a device. Thus, for example, two resistive devices and capacitive device pairs (the components of each pair coupled in series, one pair including PMOS devices and the other pair including NMOS devices) may be used to characterize a high temperature/low voltage process corner identified as an HL_RC corner. If the PMOS side is faster than the targeted or predicted speed at the given temperature and voltage, and the NMOS side is slower than targeted or predicted, the corner is referred to as an FS corner, meaning Fast/Slow or fast (relative to a target or “typical” speed) for the PMOS side, and slow (again relative to typical) for the NMOS side. The actual measured performance at a process corner can be used to determine if a device is within tolerance and will conform to a particular set of constraints.
As already noted, increases in the operational speed have continued to narrow constraints imposed upon ICs. But as the allowable deviations of the measured performance of devices at the various process corners decreases, the production yield of such ICs also tends to decrease, as it becomes increasingly difficult to control the process parameters to the resolution necessary to conform to target process corners. One solution that has been developed has been to design into ICs the ability to adjust the configuration of operational devices to compensate for variations in process corners that result from variations in processing parameters.
An example of a circuit that compensates for variations in process corners is the ZQ calibration circuit used within double data rate, version 3 (DDR3) synchronous dynamic random access memories (SDRAMs). Such a circuit adjusts the characteristic impedance of an output driver by compensating for changes in process corners associated with both active MOS devices as well as internal resistive devices. However, because resistive devices within both the calibration circuit and the compensated devices tend to be the dominant component, the resulting compensation reflects primarily the influence of process corners associated with the resistive devices. Thus, the resulting compensation may not reflect shifts in the process corners associated with the MOS devices, and in fact may compensate in a manner opposite that needed to compensate for shifts in the process corners associated with the MOS devices.